Department of Communications and Computer Engineering
Graduate School of Informatics
Kyoto 606-8501, Japan
onodera @ i.kyoto-u.ac.jp
Engineering Bld. #3, Room S302
Areas of Interest:
- Design Technology of Digital and Analog LSIs
- Design Methods for Low Power and High Speed LSIs
- Design for Manufacturability
- VLSI Architecture
- Computer-Aided Design of Digital and Analog LSIs
Hidetoshi Onodera, Masanori Hashimoto, and Tetsutaro Hashimoto,
ASIC Design Methodology with On-Demand Library Generation,
2001 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 57-60 (June 2001).
Tomohiro Fujita and Hidetoshi Onodera,
A Method for Linking Process-level Variability to System Performances,
IEICE Trans. Fundamentals, Vol.E83-A, No.12, pp. 2591-2599 (December 2000).
Masanori Hashimoto and Hidetoshi Onodera,
A Performance Optimization Method by Gate Resizing Based on Statistical Static
IEICE Trans. Fundamentals, Vol.E83-A, No.12, pp. 2558-2568 (December 2000).
Akio Hirata, Hidetoshi Onodera, and Keikichi Tamaru,
Estimation of Propagation Delay Considering Short-Circuit Current for Static CMOS Gates,
IEEE Trans. Circuits and Systems--I: Fundamental Theory and Applications, Vol.45, No.11, pp. 1194-1198 (November 1998).
Masaki Kondo, Hidetoshi Onodera, and Keikichi Tamaru,
Model-Adaptable MOSFET Parameter-Extraction Method Using an Intermediate Model,
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol.17, No.5, pp. 400-405 (May 1998).
Doctor of Engineering (Kyoto Univ.)
IEICE, IPSJ, IEEE, ACM
Integrated Circuits Engineering, Advanced.
Logic Circuits, Digital Circuits, Seminar and Practice in Electrical and Electronics Engineering: Logic Design
July 7, 2001