Kazutoshi Kobayashi
Associate Professor
Department of Communications and Computer Engineering
Graduate School of Informatics
Kyoto University
Kyoto 606-8501, Japan
Phone:
+81-75-753-5313
Fax:
+81-75-753-5343
Email:
kobayasi@i.kyoto-u.ac.jp
Office:
Engineering Bld. #3, Room S306
Areas of Interest:
- Hardware/Software Codesign using System-level Description Language
- Peak-Current Supression by Semi-synchronous Clock Distribution
- Video Compression
- Parallel Processing by Using Functional Memories
Representative Publications:
-
K.Kobayashi, M.Eguchi, T.Iwahashi, T.Shibayama, X.Li, K.Takai, H.Onodera
Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones
IEICE Transactions on Electronics, vol E84-C, no 2, pp. 193-201, (2001)
-
K.Kobayashi, M.Yamaoka, Y.Kobayashi,
H.Onodera, K.Tamaru
Architecture and Performance Evaluation of a New Functional Memory: Functioal Memory for
Addition
IEICE Transactions Fundamentals, vol E83-A, no 12, pp. 2400-2408, (2000)
-
K. Kobayashi, K. Terada, H. Onodera, K. Tamaru
A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector
Quantization
IEICE Trans. Fundamentals, vol E82-A, no 2, pp. 215-222 , 1999
- Memory Based Architecture and its Implementation Scheme Named Bit-Parallel Block-Parallel
Functional Memory Type Parallel Processor BPBP FMPP
K. Tamaru, K. Kobayashi, H. Onodera
Computers & Electrical Engineering, vol 24, pp. 17-31, (1998)
-
K. Kobayashi, H. Onodera
ST: Perl Package for Simulation and Test Environment
Proc. IEEE International Symposium on Circuits and Systems, vol V, pp. 89-92, (2001)
Academic Degree:
Doctor of Engineering (Kyoto Univ.)
Academic Society:
IEEE, Institute of Electronics, Information and Communication
Engineers(IEICE), Information Processing Society of Japan (IPSJ)
Courses
-
Graduate Courses:
Advanced Integrated Circuits.
-
Undergraduate Courses:
Electric Labratory
Further Informations:
Last modified: Thu Jul 5 09:06:17 JST 2001